1. Field of the invention
The present invention relates to a charge-pump circuit, especially the present invention relates to a charge-pump circuit used for a PLL (Phase Locked Loop) circuit.
2. Description of the Related Art
A charge-pump circuit functions to convert a phase difference between a first input signal and a second input signal into a voltage and transmits the converted voltage to another circuit. The charge-pump circuit is used, for example, to control the oscillating frequency of an internal oscillating circuit of a PLL circuit. That is, since the PLL circuit includes an internal oscillating circuit, and the oscillating frequency of the internal oscillating circuit is controlled by a charge on a capacitor provided therein, the charge-pump circuit is used to control the charge on the capacitor.
FIG. 1 shows one example of a conventional charge-pump circuit in a PLL circuit. The PLL circuit in this example generates a frequency from data bits transmitted at a known fundamental timing, and the generated frequency corresponds to the fundamental timing and is output therefrom. This PLL circuit includes a phase comparator 1, a charge-pump circuit 2 having a feeder circuit 3 and a loop filter 4, a VCO (Voltage Controlled Oscillator) 5, and a flip-flop (shown as D-F/F in FIG. 1). A capacitor which is not shown in FIG. 1 is provided in the loop filter 4.
In the PLL circuit as shown in FIG. 1, an input signal R1 and a frequency from VCO 5 are compared by the phase comparator 1, the resulting signals U1 and D1, after phase comparison, are input to the feeder circuit 3 of the charge-pump circuit 2 as a first drive signal and a second drive signal, and the capacitor in the loop filter 4 is charged in accordance with the difference of the phase between the input signal R1 and the oscillating frequency of VCO 5. Then the voltage across the capacitor is fed to the VCO 5, and the frequency of the VCO 5 is changed in accordance with the voltage level of the capacitor. The output signal from the VCO 5 is input to the flip-flop 6 as a clock signal, and the flip-flop 6 generates the data from the input signal R1 on the basis of the clock signal.
FIG. 2 shows a concrete conventional circuit diagram consisting of the phase comparator 1 and the charge-pump circuit 2 as shown in FIG. 1. The phase comparator 1 has a plurality of NAND circuits, and outputs pulse signals U1 and D1, having negative polarity, in accordance with the input signals R1 and V1. The negative pulses in the output signals U1 and D1 are not input to the charge-pump circuit 2 at the same time. Either one negative pulse, from either the output signal U1 or the output signal D1, is input to the charge-pump circuit 2, or no negative pulse is input to the charge-pump circuit 2. The charge-pump circuit 2 has the following elements: feeder circuit 3 comprised of bipolar transistors; MOS transistors TR2 and a bipolar transistor TR1 act as switching elements; and a loop filter 4 having a capacitor C which stores a voltage. There is a phase difference between the first drive signal U1 and the second drive signal D1, but both have a negative polarity and both are input to the charge-pump circuit 2 from the phase comparator 1.
FIGS. 3 to 6 are waveform diagrams showing input signals R1 and V1 input to the phase comparator 1; signals at points a, b, and c in the phase comparator 1; and output signals U1 and D1 to the charge-pump circuit 2.
FIG. 3 shows waveform diagrams at particular points a, b, and c in the phase comparator 1 and the charge-pump circuit 2 in FIG. 2 when the initial value of the point a is 0 and the point b is 0, and the phase of the input signal R1 lags compared to the phase of the input signal V1.
FIG. 4 shows waveform diagrams at particular points a, b, and c in the phase comparator 1 and the charge-pump circuit 2 in FIG. 2 when the initial value of the point a is 0 and the point b is 1, and the phase of the input signal R1 lags compared to the phase of the input signal V1.
FIG. 5 shows waveform diagrams at particular points a, b, and c in the phase comparator 1 and the charge-pump circuit 2 in FIG. 2 when the initial value of the point a is 1 and the point b is 0, and the phase of the input signal R1 lags compared to the phase of the input signal V1.
FIG. 6 shows waveform diagrams at particular points a, b, and c in the phase comparator 1 and the charge-pump circuit 2 in FIG. 2 when the initial value of the point a is 1 and the point b is 1, and the phase of the input signal R1 lags compared to the phase of the input signal V1.
As is understood from four waveform diagrams shown in FIGS. 3 to 6, a negative pulse having a width corresponding to the amount of phase lag appears, and the width of the second drive signal D1 equals the width of the negative pulse, when the phase of the input signal R1 lags compared to the phase of the input signal V1. Conversely, a negative pulse having a width corresponding to the amount of phase lead appears by the symmetry of the circuit as shown in FIG. 2, and the width of the first drive signal U1 equals the width of the negative pulse, when the phase of the input signal R1 leads compared to the phase of the input signal Vl.
Next, the operation of the charge-pump circuit 2, to which the first and the second drive signals U1 and D1, as negative pulses, are input, is explained. First, when the first drive signal U1 changes from a high level to a low level at the input to the charge-pump circuit 2, the following operations occur: transistor TR3 turns ON; loop-filter 4 is activated; a current I1 flows to a capacitor C in the direction as shown by the arrow; the capacitor C is charged in accordance with drive time by the first drive signal U1 (the time between the drive signal U1 changing from a high level to a low level and returning to a high level, that is, equal to the width of the negative pulse); and a voltage appears at the terminal of the capacitor C.
Next, when the second drive signal D1 changes from a high level to a low level at the input to the charge-pump circuit 2, the following operations occur: transistor TR5 turns ON; transistor TR4 turns ON; transistor TR1 in the loop-filter 4 is activated; transistor TR2 is activated after the transistor TR1 turns on; a current I2 flows to a capacitor C in the direction as shown by the arrow; the capacitor C is charged in accordance with driving time by the first drive signal D1 (the time between the drive signal D1 changing from a high level to a low level and returning to a high level, that is, equal to the width of the negative pulse); and a voltage appears at the terminal of the capacitor C.
As described above, the current flowing to the capacitor C is inverted at every input of the negative pulse included in the first drive signal U1 and the second drive signal D1, and the voltage is charged in the capacitor in accordance with the difference between the timing of the first drive signal U1 and the second drive signal D1. By the way, it is necessary to prevent leakage of the charge from the capacitor through the control terminal of the transistor TR1 which functions as a switching element, when neither the first drive signal U1 nor the second drive signal D1 are input to the charge-pump circuit 2. Accordingly, a MOS transistor, whose control terminal has a high input impedance, is used as the transistor TR1 in the conventional charge-pump circuit to prevent the leakage of the charge from the capacitor C.
However, the conventional charge-pump circuit has the following problems, such as a high number of elements are mounted on the printed circuit board, and the mounting density of the circuit elements on the printed circuit board is decreased. The reasons for these problems are as follows: a part A, surrounded by a dashed line in FIG. 2, is not formed as an IC (Integrated Circuit); circuit elements such as transistors, a capacitor, and resistors are mounted on an external printed circuit board; a charge-pump circuit is constructed by connecting these elements via a printed circuit;
As a countermeasure to this problem, an attempt has been made to decrease the area of the circuit elements by combining a MOS transistor TR1 with the other circuit elements and forming an IC, to decrease the number of circuit elements. One way to make an IC is to form every circuit element by MOS technology, and the other way is to form the IC by Bi-MOS technology.
The way to form every circuit element by MOS technology has the merit of decreasing the manufacturing cost, but it has the problem that it cannot realize a high-speed circuit. The way to form the IC by Bi-MOS technology has the merit of realizing a high-speed circuit, but it has the problem that the manufacturing cost thereof will increase since the process of making a capacitor and a resistor and the process of making a transistor are not the same.